1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for planarizing an insulating interlayer to be used in conjunction with other multilevel interconnect technology.
2. Description of the Prior Art
To manufacture an integrated circuit, it is necessary to form many active devices on a single substrate. Initially, each of the devices must be isolated from the others, but recently it has become necessary to electrically interconnect specific devices during the fabrication step to obtain the desired functionality of the circuit. Both MOS and bipolar devices have multilevel interconnect structures to accommodate the numerous interconnections of the devices.
As the number of layers in an interconnect structure increase, the topography of the top layer coated on the semiconductor wafer becomes more rugged. For example, in manufacturing a semiconductor wafer having two or more metal layers formed thereon, a first insulating interlayer is coated on the wafer on which a plurality of oxide layers, polycrystalline silicon conductive layers, and a first metal wiring layer, have been previously formed, followed by forming vias for interposing a second metal layer. The surface of the first insulating layer is uneven because the underlying structure upon which the first insulating layer has been formed is uneven. When a second metal layer is directly formed over such a first insulating interlayer, the second metal layer fractures due to peaks and/or cracks in the first insulating intedayer and as a result the metal coverage over the first insulating interlayer fails. This failure lowers the yield of the semiconductor device. Therefore, planarization of the insulating interlayer is required for multilevel metal interconnections, before forming a via or coating a second metal layer.
One method available for planarizing the semiconductor wafer is to form a first conformal silicon oxide layer over the underlying irregular structures. Next, a planarizing spin-on-glass (SOG) layer is formed over the first silicon oxide layer. The SOG layer is then baked and cured. The SOG layer is etched back to remove most or all of the SOG layer and a portion of the first oxide layer. This etch back step is used to transfer the planar SOG top surface shape to the first oxide surface. The etch of the SOG layer and the silicon oxide layer is controlled so that they both etch at about the same rate. Next, a second silicon oxide layer can be formed over the first silicon oxide layer. Many variations on this SOG etch back method exist.
However, the current planarization processes do not provide an uniform planar surface which results in an oxide thickness variation across a wafer and a surface with peaks and valleys. The non-planar surface is caused by at least two problems. First, the etchback rate of the SOG is faster near the edge of the wafer compared to the center of the wafer. This causes more of the SOG and first oxide layer to be etched back more at the edges of the wafer than the center area. The end result is that the resulting surface is lower (thinner) at the outside areas compared to the center areas. This non-uniformity may lead to several problems, such as tungsten residue and metal bridging for the next overlying metal layer.
Second, the spinning process used to form the SOG layer normally deposits the SOG layer thicker in the wafer center than near the wafer edge. As shown in FIG. 1, first insulating layer 12 and a SOG layer 14 are formed over a substrate 10. This convex shaped SOG layer 14 is created by the spin on process where centripetal forces cause the SOG layer to thin the further from the wafer center. See FIG. 1. Next, the SOG layer 14 and the first insulating layer 12 are etched back. Because of the thinner SOG layer in the periphery, the underlying silicon oxide layer 12 is etched back more and is thinner in the peripheral areas. For example, for an etch back of a 6000 .ANG. SOG layer 14 and a 1500 .ANG. etch into an underlying silicon oxide layer 12, the typical silicon oxide layer thickness difference between the center and the periphery caused by the non-uniform etch back and SOG spin will be between 1500 to 2000 .ANG..
The combination of the two problems, the faster SOG etch rate on the periphery of the wafer and the thinner SOG layer on the periphery of the wafer, creates a non-uniform and non-planar surface. The underlying silicon oxide layer is thinner in the peripheral areas. This non-planar surface can cause tungsten residue problems. Tungsten residue from subsequent metal processes can remain in the valleys on the non-planar surface and cause shorting between metal lines thus reducing chip yields.
U.S. Pat. No. 4,676,867, to Elkins and U.S. Pat. No. 4,986,878 to Malazgirt, describe SOG etchback processes, but do not adequately improve the SOG etchback uniformity. Elkin teaches a process of applying a first direction layer over a first metal layer, applying a spin-on-glass layer over the first dielectric layer, etching the spin-on-glass layer to reveal parts of the first dielectric layers. A second dielectric layer is formed over the first dielectric layer. However, this process does not address the problems of the non-uniform spin-on-glass layer and the non-uniform etch back.
Malazgrit teaches an etch back process where a dialectic layer is formed over a structure, a spin-on-glass layer is applied over the dialectic layer, the spin-on-glass layer and portions of the dialectic layer are etched away, the remaining spin-on-glass layer is removed with an etch, and a passivation layer is applied over the remaining dielectric layer. However, further improvement is required to overcome the problems of the uneven SOG layer and etch back.
Therefore, it is desirable to develop a SOG etch back process that provides improved etch back uniformity and improved planar resulting surface.